Truth Table Generator
Enter a Boolean expression using variables A–Z. Supported operators: . * & AND · + | OR · ! ~ ' NOT · ^ XOR · juxtaposition (AB) also means AND.
Boolean Simplifier
Minimizes any Boolean expression to its simplest Sum-of-Products and Product-of-Sums forms using the Quine–McCluskey algorithm.
K-map Solver
Click a cell to cycle 0 → 1 → X (don't care) → 0. The minimized SOP expression and its prime implicants update live.
Logic Gate Simulator
Add gates, drag them into place, then drag from an output pin (right) to an input pin (left) to wire them. Click an INPUT node to toggle 0/1.
CMOS Gate Designer
Pull-up (PMOS) and pull-down (NMOS) switching networks for standard-cell logic gates, drawn as stick schematics between VDD and GND.
Verilog Generator
Turn a Boolean expression into synthesizable Verilog — as a dataflow assign, a behavioral case block, or a structural gate-level netlist.
Verilog Simulator
Paste synthesizable Verilog (ports + assign statements and/or primitive gate instances). It's parsed into a signal netlist you can drive interactively.
Timing Analyzer
Estimate propagation delay from per-gate delay figures — either as a quick chain calculator, or as the true critical path through your Logic Gate Simulator circuit.
Power Calculator
Estimate dynamic (switching) and static (leakage) power using Pdyn = αCV²f and Pstatic = V·Ileak.
RTL Viewer
A port-level block diagram of the module currently defined in the Verilog Generator, plus the internal gate-level netlist when one has been exported.